//////////////////////////////////////////////////////////////////////////////////
// INSTITUTION:    Xidian University
// DESIGNER:       Yuan Xiaoguang & Ren Aifeng    
// 
// Create Date:    16:53:58 02/14/2016 
// Design Name:    PWM_COMPARATOR
// Module Name:    PWM_COMPARATOR
// Project Name:   PWM
// Target Devices: EP3C16F484C6
// Tool versions:  Quartus II 13.1
// Design Lauguage:Verilog-HDL
// Dependencies:   -
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: if i_compare_value < i_compare_set_value o_compare_result = 1
//                      otherwise o_compare_result = 0
//
//////////////////////////////////////////////////////////////////////////////////
module PWM_COMPARATOR (
									input 	 [6:0]   i_compare_value,
									input		 [6:0]	i_compare_set_value,
									output reg			o_compare_result
								);
												
always @ (i_compare_value or i_compare_set_value)
begin
	if( i_compare_value < i_compare_set_value  )begin
		o_compare_result <= 1'b1;
	end else begin
		o_compare_result <= 1'b0;		
	end
end

endmodule
